1. Field of the Invention
The invention relates to design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for analyzing a power supply network in a design of an integrated circuit.
2. Related Art
A power supply network that is to be built in an integrated circuit die can be analyzed in any of a number of different ways known in the prior art. U.S. Pat. No. 5,598,348 granted to Rusu et al. on Jan. 28, 1997 entitled “Method and apparatus for analyzing the power network of a VLSI circuit” is incorporated by reference herein in its entirety. This patent describes extracting the power network and then deriving a compacted power network including a compacted primary resistive network to characterize the electrical resistance of power trunks within the semiconductor circuit layout. The compacted power network is simulated to identify areas that do not comply with predetermined criteria, such as electromigration limits and voltage drop limits. The layout may be reconfigured to satisfy the limits.
U.S. Pat. No. 6,675,139 granted to Jetton et al. on Jan. 6, 2004 entitled “Floor plan-based power bus analysis and design tool for integrated circuits” is also incorporated by reference herein in its entirety. This patent states, as background, that post-layout simulation takes a long time to complete (typically several days) and on completion may indicate problems with excessive voltage drop and electromigration. Finding such problems after post-layout simulation requires the designer to change the IC floor plan and re-run the layout and post-layout simulation, which adds days, if not weeks, to the design cycle. In addition, post-layout simulation time makes testing and comparing several different power-bus grid designs extremely time consuming. This problem is conventionally solved by over-estimating a circuit's power requirements but this is a sub-optimal use of the IC's available silicon core space.
U.S. Pat. No. 6,675,139 proposes a solution to the problems described in the previous paragraph as follows: mapping wire segments forming the power-bus grid to the integrated circuit core, specifying at least one power zone in the integrated circuit core, calculating a current density and voltage drop in the wire segments with respect to the power zone, and displaying the current density and voltage drop in the wire segments.
U.S. Pat. No. 6,446,245 granted to Xing et al. on Sep. 3, 2002 and entitled “Method and Apparatus for performing power routing in ASIC design” is incorporated by reference herein in its entirety. This patent states that traditionally power routing is performed during the floor planning stage, before cell placement, and for this reason the location of the standard cells and hence the power consumption behavior is not known at the power routing stage. Also this design flow creates obstacles for cell placement optimization. Therefore, this patent describes a method in which standard cells are placed in the physical layout prior to power routing, and they are placed in a bottom-up hierarchical manner.
U.S. Pat. No. 6,311,147 granted to Tuan et al. on Oct. 30, 2001 entitled “Integrated circuit power net analysis” is incorporated by reference herein in its entirety. This patent uses a circuit simulator to determine current values for integrated circuit devices at specified supply voltages. A power net simulator uses the current values to calculate various characteristics such as voltage drop, current density and ground bounce. A layout representation of the power net is shown on a computer display along with user-specified characteristics.
U.S. Pat. No. 6,523,154 granted to Cohn et al. on Feb. 18, 2003 entitled “Method for supply voltage drop analysis during placement phase of chip design” is incorporated by reference herein in its entirety. This patented method provides a library of circuits for use in designing an integrated circuit chip and determines a supply current requirement and an operating voltage range for each circuit in the circuit library. The method then includes calculating an admittance matrix representing the power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid, assigning regions of the power grid to each of the ports, and placing a set of circuits from the circuit library in regions on the power grid. The method further includes calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions, calculating a node voltage at each of the ports by solving a system of linear equations corresponding to the calculated admittance matrix, imposing a penalty to each node having a node voltage outside of a predetermined range, and calculating the node voltages and the penalties to a cost-based floorplanning/placement analysis tool.